Using well known techniques, integrated circuits ("ICs") are fabricated on a substrate by forming various depositions, layer by layer. For example, an IC containing metal-oxide-semiconductor ("MOS") devices has a thin layer of oxide over which a layer of gate material (e.g., polysilicon) is deposited and then defined. The MOS device source and drain regions are then formed, either by photolithography or by using the defined gates as a self-aligning mask.
Normal backend processing that forms electrical interconnects completes the fabrication of the IC. The IC is then functionally tested to detect and screen-out defective units, which should not be assembled and delivered to customers.
For a variety of reasons, defects can exist randomly anywhere within the IC structure being fabricated. In ICs containing MOS devices, the thin gate oxide is a substantial factor contributing to failures, among other causes, such as metal electron migration or particulates.
While some defects manifest failure during the functionality test, other defects survive the functionality test, but can cause the premature failure ("infant mortality") of the completed IC. Infant mortality refers to completed, apparently good, devices that fail within about 20% of the expected mean time between failures ("MTBF").
Initially, ICs containing weak oxide (e.g., gate oxide with defects) will function normally. However after the completed IC has been operated sufficiently long, stress sufficient to wear-out weak gate oxide accumulates, which causes the IC to fail. Statistically, IC failure typically has a bimodal distribution failure pattern: ICs either fail very soon after actual operation in the field (infant mortality), or survive essentially forever.
To promote good product quality, manufacturers wish to weed-out completed ICs that are destined to fail prematurely in the field. Thus, ICs are subjected to post-fabrication burn-in and stress procedures. Ideally such procedures will accelerate the effects of defects, forcing failures to appear so that ICs containing defects will fail during such procedures. Such devices are then screened-out, rather than delivered to customers, where-upon the devices will fail prematurely after operation in the field. Typical prior art screening procedures are described in the text "Integrated Circuit Engineering" by Glaser and Subak-Sharpe, published by Edison-Westley (May 1979) . In the prior art, burn-in typically involves subjecting the completed ICs to a temperature of about 100.degree. C. to 150.degree. C., for perhaps 24 to 96 hours, with power supply voltages being applied to the IC at about 160% nominal voltage. If desired, ambient pressure and humidity may also be varied.
The increased temperature and power supply levels should accelerate stress resulting from any defects, thereby causing ICs containing such defects to fail during burn-in. In practice, most of the integrated circuit input ports are maintained at a fixed (DC) voltage. Alternatively, other procedures present a simple vector (AC) voltage pattern to the integrated circuit input ports to change internal device node voltages, thereby increasing the number of transistors subjected to stress.
Unfortunately, because these prior art procedures subject ICs to stress after fabrication is complete, it is not always possible to effectively stress every single transistor in each integrated circuit. For example, physical inaccessible may prevent applying over-voltage directly to some transistors. Other transistors, while accessible, may require very complicated vector patterns involving longer burn-in time and expensive equipment.
Thus prior art post-fabrication stressing tends to be either simple but inadequate, or expensive and time consuming. In either event, prior art procedures fail to realistically stress all devices on a completed IC. The result is that many defect-containing ICs are inadequately stressed, and therefore survive burn-in and functionality testing, only to fail prematurely in the field due to infant mortality.
What is needed is an improved method to more effectively stress the gate oxide of every device on an IC wafer. Preferably such method should apply stress on a per-wafer basis to 100% of the gate oxide. Further, such method should be applicable before IC fabrication has been completed. The present invention discloses such method.